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C515C Datasheet

  • C515C

  • 8-Bit CMOS Microcontroller

  • 1124.47KB

  • Infineon   Infineon

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C515C
Timer / Counter 0 and 1
Timer/Counter 0 and 1 can be used in four operating modes as listed in
table 6
:
Table 6
Timer/Counter 0 and 1 Operating Modes
Mode
0
1
2
3
Description
8-bit timer/counter with a
divide-by-32 prescaler
16-bit timer/counter
8-bit timer/counter with
8-bit autoreload
Timer/counter 0 used as one
8-bit timer/counter and one
8-bit timer / Timer 1 stops
TMOD
M1
0
0
1
1
M0
0
1
0
1
Timer/Counter Input Clock
internal
external (max)
f
OSC
/6 x 32
f
OSC
/12 x 32
f
OSC
/6
f
OSC
/12
In the 鈥渢imer鈥?function (C/T = 鈥?鈥? the register is incremented every machine cycle. Therefore the
count rate is
f
OSC
/6.
In the 鈥渃ounter鈥?function the register is incremented in response to a 1-to-0 transition at its
corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a
falling edge the max. count rate is
f
OSC
/12. External inputs INT0 and INT1 (P3.2, P3.3) can be
programmed to function as a gate to facilitate pulse width measurements.
Figure 11
illustrates the
input clock logic
OSC
梅6
C/T = 0
f
OSC
/6
Timer 0/1
Input Clock
C/T = 1
P3.4/T0
P3.5/T1
TR0
TR1
_
<1
Control
&
Gate
(TMOD)
P3.2/INT0
P3.3/INT1
=1
MCS03117
Figure 11
Timer/Counter 0 and 1 Input Clock Logic
Semiconductor Group
33
1997-07-01

C515C PDF文件相關(guān)型號

SAB-C515C-8RM,SAB-C515C-LM,SAF-C515C-8RM,SAF-C515C-LM

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