C515C
Reset and System Clock
The reset input is an active low input at pin RESET. Since the reset is synchronized internally, the
RESET pin must be held low for at least two machine cycles (12 oscillator periods) while the
oscillator is running. A pullup resistor is internally connected to
V
CC
to allow a power-up reset with
an external capacitor only. An automatic reset can be obtained when
V
CC
is applied by connecting
the RESET pin to
V
SS
via a capacitor.
Figure 6
shows the possible reset circuitries.
Figure 6
Reset Circuitries
Figure 7
shows the recommended oscillator circiutries for crystal and external clock operation.
Figure 7
Recommended Oscillator Circuitries
Semiconductor Group
19
1997-07-01