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DS1801 Datasheet

  • DS1801

  • Dual Audio Taper Potentiometer

  • 229.11KB

  • Dallas   Dallas

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DS1801
AC ELECTRICAL CHARACTERISTICS
PARAMETER
CLK Frequency
Width of CLK Pulse
Data Setup Time
Data Hold Time
Propagation Delay Time
Low to High Level
Clock to Output
Propagation Delay Time
Low to High Level
RST
High
(-40擄C to +85擄C; V
CC
=2.7V to 5.5V)
TYP
MAX
10
UNITS
MHz
ns
ns
ns
50
ns
NOTES
7
7
7
7
7
SYMBOL
f
CLK
t
CH
t
DC
t
CDH
t
PLH
MIN
DC
50
30
10
t
PLH
t
CC
t
HLT
t
CR
t
RLT
200
50
50
50
ns
ns
ns
7
7
7
7
7
to Clock Input High
Clock Input High
RST
Low to
CLK Rise Time
RST
60
ns
ns
Inactive
NOTES:
1. All voltages are referenced to ground.
2. Valid for V
CC
= 2V only.
3. Capacitance values apply at 25擄C.
4. Inter-channel matching is used to determine the relative voltage difference in dB between the same
tap position on each potentiometer. The DS1801 is specified for
鹵0.5
dB inter-channel matching.
5. Tap-to-tap tolerance is used to determine the change in voltage between successive tap positions. The
DS1801 is specified for
鹵0.25
dB tap-to-tap tolerance.
6. Typical values are for T
A
=25擄C and nominal supply voltage.
7. See Figure 3.
8. Absolute tolerance is used to determine measured wiper voltage vs. expected wiper voltage as
determined by wiper position. The DS1801 is bounded by a
鹵1
dB absolute tolerance.
9. Maximum current specifications are based on clock rate and active zero-crossing detection. See
Figure 5 for clock rate vs. current specification.
10. See Figure 7.
11. Standby current levels apply when all inputs are driven to appropriate supply levels.
12. These parameters are characterized and not 100% tested.
13. Valid at 25擄 C only.
9 of 10

DS1801 產(chǎn)品屬性

  • Lead (SnPb) Finish for COTSObsolescence Mitigation Program

  • 25

  • 集成電路 (IC)

  • 數(shù)據(jù)采集 - 數(shù)字電位器

  • -

  • 64

  • 45k

  • 2

  • 標(biāo)準(zhǔn)值 750 ppm/°C

  • 易失

  • 3 線串口

  • 2.7 V ~ 5.5 V

  • -40°C ~ 85°C

  • 通孔

  • 14-DIP（0.300"，7.62mm）

  • 14-PDIP

  • 管件

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