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DS1746 Datasheet

  • DS1746

  • Y2KC Nonvolatile Timekeeping

  • Dallas   Dallas

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DS1746/DS1746P
DS1746 REGISTER MAP
Table 2
ADDRESS
DATA
B
7
B
6
X
X
FT
X
1FFFF
1FFFE
X
1FFFD
X
1FFFC
BF
1FFFB
X
1FFFA
X
1FFF9
OSC
1FFF8
W
OSC = STOP BIT
W = WRITE BIT
R
B
5
B
4
B
3
B
2
B
1
10 YEAR
YEAR
X
10 MO
MONTH
10 DATE
DATE
X
X
X
DAY
10 HOUR
HOUR
10 MINUTES
MINUTES
10 SECONDS
SECONDS
10 CENTURY
CENTURY
R = READ BIT
X = SEE NOTE BELOW
B
0
FUNCTION/RANGE
YEAR
00-99
MONTH
01-12
DATE
01-31
DAY
01-07
HOUR
00-23
MINUTES
00-59
SECONDS
00-59
CENTURY
00-39
FT = FREQUENCY TEST
BF = BATTERY FLAG
NOTE:
All indicated 鈥淴鈥?bits are not dedicated to any particular function and can be used as normal RAM bits.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1746 is in the read mode whenever OE (output enable) is low, WE (write enable) is high, and CE
(chip enable) is low. The device architecture allows ripple-through access to any of the address locations
in the NV SRAM. Valid data will be available at the DQ pins within t
AA
after the last address input is
stable, providing that the CE and OE access times and states are satisfied. If CE or OE access times
and states are not met, valid data will be available at the latter of chip enable access (t
CEA)
or at output
enable access time (t
OEA)
. The state of the data input/output pins (DQ) is controlled by CE and OE . If the
outputs are activated before t
AA
, the data lines are driven to an intermediate state until t
AA
. If the address
inputs are changed while CE and OE remain valid, output data will remain valid for output data hold
time (t
OH
) but will then go indeterminate until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1746 is in the write mode whenever WE , and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE , or CE . The addresses must be held valid throughout
the cycle. CE or WE must return inactive for a minimum of t
WR
prior to the initiation of another read or
write cycle. Data in must be valid t
DS
prior to the end of write and remain valid for t
DS
afterward. In a
typical application, the OE signal will be high during a write cycle. However, OE can be active
provided that care is taken with the data bus to avoid bus contention. If OE is low prior to
WE transitioning low the data bus can become active with read data defined by the address inputs. A low
transition on WE will then disable the output t
WEZ
after WE goes active.
5 of 18

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