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M12L16161A-4.3T Datasheet

  • M12L16161A-4.3T

  • 512K x 16Bit x 2Banks Synchronous DRAM

  • 27頁(yè)

  • ETC

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M12L16161A
512K x 16Bit x 2Banks Synchronous DRAM
FEATURES
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GENERAL DESCRIPTION
JEDEC standard 3.3V power supply
The M12L16161A is 16,777,216 bits synchro-
LVTTL compatible with multiplexed address
nous high data rate Dynamic RAM organized as
Dual banks operation
2 x 524,288 words by 16 bits, fabricated with
MRS cycle with address key programs
high performance CMOS technology. Synchro-
- CAS Latency (2 & 3 )
nous design allows precise cycle control with the
- Burst Length (1, 2, 4, 8 & full page)
use of system clock I/O transactions are possible
- Burst Type (Sequential & Interleave)
on every clock cycle. Range of operating fre-
All inputs are sampled at the positive going edge quencies, programmable burst length and pro-
grammable latencies allow the same device to be
of the system clock
Burst Read Single-bit Write operation
useful for a variety of high bandwidth, high
performance memory system applications.
DQM for masking
Auto & self refresh
32ms refresh period (2K cycle)
ORDERING INFORMATION
Part NO.
M12L16161A-4.3T
M12L16161A-5T
M12L16161A-5.5T
M12L16161A-6T
M12L16161A-7T
M12L16161A-8T
MAX Freq.
233MHz
200MHz
183MHz
166MHz
143MHz
125MHz
Interface
Package
LVTTL
50
TSOP(II)
PIN CONFIGURATION (TOP VIEW)
V
DD
DQ0
DQ1
V
SSQ
DQ2
DQ3
V
DDQ
DQ4
DQ5
V
SSQ
DQ6
DQ7
V
DDQ
LDQM
WE
CAS
RAS
CS
BA
A10/AP
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
V
SS
DQ15
DQ14
V
SSQ
DQ13
DQ12
V
DDQ
DQ11
DQ10
V
SSQ
DQ9
DQ8
V
DDQ
N.C/RFU
UDQM
CLK
CKE
N.C
A9
A8
A7
A6
A5
A4
V
SS
50PIN TSOP(II)
(400mil x 825mil)
(0.8 mm PIN PITCH)
Elite Semiconductor Memory Technology Inc.
P.1
Publication Date : Jan. 2000
Revision : 1.3u

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