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K4H560838D-NC/LA0 Datasheet

  • K4H560838D-NC/LA0

  • 256Mb sTSOPII

  • 18頁

  • SAMSUNG   SAMSUNG

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256Mb sTSOPII
DDR SDRAM
Key Features
鈥?Double-data-rate architecture; two data transfers per clock cycle
鈥?Bidirectional data strobe(DQS)
鈥?Four banks operation
鈥?Differential clock inputs(CK and CK)
鈥?DLL aligns DQ and DQS transition with CK transition
鈥?MRS cycle with address key programs
-. Read latency 2, 2.5 (clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
鈥?All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
鈥?Data I/O transactions on both edges of data strobe
鈥?Edge aligned data output, center aligned data input
鈥?DM for write masking only
鈥?Auto & Self refresh
鈥?7.8us refresh interval(8K/64ms refresh)
鈥?Maximum burst refresh cycle : 8
鈥?54pin sTSOP II package
ORDERING INFORMATION
Part No.
K4H560438D-NC/LB3
K4H560438D-NC/LA2
K4H560438D-NC/LB0
K4H560438D-NC/LA0
K4H560838D-NC/LB3
K4H560838D-NC/LA2
K4H560838D-NC/LB0
K4H560838D-NC/LA0
32M x 8
64M x 4
Org.
Max Freq.
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
A0(DDR200@CL=2)
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
A0(DDR200@CL=2)
SSTL2
54pin sTSOP II
SSTL2
54pin sTSOP II
Interface
Package
Operating Frequencies
- B3(DDR333)
Speed @CL2
Speed @CL2.5
DLL jitter
*CL : Cas Latency
133MHz
166MHz
鹵0.7ns
- A2(DDR266A)
133MHz
133MHz
鹵0.75ns
- B0(DDR266B)
100MHz
133MHz
鹵0.75ns
- A0(DDR200)
100MHz
-
鹵0.8ns
- 1 -
Rev.0.0 May. 鈥?/div>
02

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