256Mb
Key Features
鈥?Double-data-rate architecture; two data transfers per clock cycle
鈥?Bidirectional data strobe(DQS)
鈥?Four banks operation
鈥?Differential clock inputs(CK and CK)
鈥?DLL aligns DQ and DQS transition with CK transition
鈥?MRS cycle with address key programs
-. Read latency 2, 2.5 (clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
鈥?All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
鈥?Data I/O transactions on both edges of data strobe
鈥?Edge aligned data output, center aligned data input
鈥?LDM,UDM/DM for write masking only
鈥?Auto & Self refresh
鈥?7.8us refresh interval(8K/64ms refresh)
鈥?Maximum burst refresh cycle : 8
鈥?60 Ball FBGA package
DDR SDRAM
ORDERING INFORMATION
Part No.
K4H560438D-GC(L)B3
K4H560438D-GC(L)A2
K4H560438D-GC(L)B0
K4H560838D-GC(L)B3
K4H560838D-GC(L)A2
K4H560838D-GC(L)B0
K4H561638D-GC(L)B3
K4H561638D-GC(L)A2
K4H561638D-GC(L)B0
16M x 16
32M x 8
64M x 4
Org.
Max Freq.
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
SSTL2
60 ball FBGA
SSTL2
60 ball FBGA
SSTL2
60 ball FBGA
Interface
Package
Operating Frequencies
- B3(DDR333)
Speed @CL2
Speed @CL2.5
133MHz
166MHz
- A2(DDR266A)
133MHz
133MHz
- B0(DDR266B)
100MHz
133MHz
*CL : Cas Latency
- 1 -
Rev. 2.2 Mar. 鈥?3