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K3S7V2000M-TC Datasheet

  • K3S7V2000M-TC

  • 64M-Bit (4Mx16 /2Mx32) Synchronous MASKROM

  • 27頁(yè)

  • SAMSUNG   SAMSUNG

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K3S7V2000M-TC
64M-Bit (4Mx16 /2Mx32) Synchronous MASKROM
FEATURES
鈥?/div>
JEDEC standard 3.3V power supply
鈥?/div>
LVTTL compatible with multiplexed address
鈥?/div>
Address: Row address: RA
0
~ RA
12
Column address: CA
0
~ CA
7
(x32): CA
0
~ CA
8
(x16)
鈥?/div>
Switchable organization
4,194,304 x 16(word mode) /
2,097,152 x 32(double word mode)
鈥?/div>
All inputs are sampled at the rising edge of the system clock
鈥?/div>
Read Performance at memory point of view
@33MHz 4-1-1-1 (RAS Latency=1, CAS Latency=3)
@50MHz 5-1-1-1 (RAS Latency=1, CAS Latency=4)
@66MHz 5-1-1-1 (RAS Latency=1, CAS Latency=4)
@83MHz 7-1-1-1 (RAS Latency=2, CAS Latency=5)
@100MHz 7-1-1-1 (RAS Latency=2, CAS Latency=5)
鈥?/div>
t
SAC
: 6ns
鈥?/div>
Default mode by user requirement
鈥?/div>
MRS cycle with address key programs
-. RAS Latency(1 & 2)
-. CAS Latency(3 ~ 6)
-. Burst Length : 4, 8
-. Burst Type : Sequential & Interleaved
鈥?/div>
DQM for data-out masking
鈥?/div>
Package :86TSOP2 - 400
Synch. MROM
GENERAL DESCRIPTION
The K3S7V2000M-TC is a synchronous high bandwidth mask
programmable ROM fabricated with SAMSUNG鈥瞫 high perfor-
mance CMOS process technology and is organized either as
4,194,304 x16bit(word mode) or as 2,097,152 x32bit(double
word mode) depending on polarity of WORD pin.(see pin func-
tion description). Synchronous design allows precise cycle con-
trol, with the use of system clock, I/O transactions are possible
on every clock cycle. Range of operating frequencies, program-
mable burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high perfor-
mance memory system applications.
ORDERING INFORMATION
Part NO.
K3S7V2000M-TC10
K3S7V2000M-TC12
K3S7V2000M-TC15
K3S7V2000M-TC20
K3S7V2000M-TC30
MAX Freq.
100MHz
83MHz
66MHz
50MHz
33MHz
LVTTL
86TSOP2
Interface
Package
FUNCTIONAL BLOCK DIAGRAM
Q0
Q16
.
Output
.
.
Buffer
Q15
Q31
Row Decoder
Sense AMP.
Row Buffer
4M x 16 /2M x 32
Cell Array
Address Register
CLK
ADD
Column Decoder
Col. Buffer
LRAS
Latency & Burst Length
LCKE
LRAS
LMR
LCAS
Timing
CLK
CKE
MR
Register
RAS
Programming Register
CAS
CS
DQM
*
Samsung Electronics reserves the right to
change products or specification without notice.

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